diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2017-09-07 13:54:53 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-09-07 13:54:53 +0100 |
| commit | 62c58ee0b24eafb44c06402fe059fbd7972eb409 (patch) | |
| tree | af7e6106d118cefe157af3c60b3c1be7e92db0cf /target/arm/machine.c | |
| parent | 4125e6feb71c810ca38f0d8e66e748b472a9cc54 (diff) | |
target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M
Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security
extensions are enabled.
We can freely add more items to vmstate_m_security without
breaking migration compatibility, because no CPU currently
has the ARM_FEATURE_M_SECURITY bit enabled and so this
subsection is not yet used by anything.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1503414539-28762-14-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/machine.c')
| -rw-r--r-- | target/arm/machine.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/target/arm/machine.c b/target/arm/machine.c index 80942d60fb..0017ea0416 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -225,10 +225,10 @@ static const VMStateDescription vmstate_pmsav8 = { .minimum_version_id = 1, .needed = pmsav8_needed, .fields = (VMStateField[]) { - VMSTATE_VARRAY_UINT32(env.pmsav8.rbar, ARMCPU, pmsav7_dregion, 0, - vmstate_info_uint32, uint32_t), - VMSTATE_VARRAY_UINT32(env.pmsav8.rlar, ARMCPU, pmsav7_dregion, 0, - vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_NS], ARMCPU, pmsav7_dregion, + 0, vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_NS], ARMCPU, pmsav7_dregion, + 0, vmstate_info_uint32, uint32_t), VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU), VMSTATE_END_OF_LIST() @@ -257,6 +257,10 @@ static const VMStateDescription vmstate_m_security = { VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU), VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU), + VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_S], ARMCPU, pmsav7_dregion, + 0, vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dregion, + 0, vmstate_info_uint32, uint32_t), VMSTATE_END_OF_LIST() } }; |