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authorPeter Maydell <peter.maydell@linaro.org>2017-09-14 18:43:16 +0100
committerPeter Maydell <peter.maydell@linaro.org>2017-09-14 18:43:16 +0100
commitdc3c4c14f0f12854dbd967be3486f4db4e66d25b (patch)
tree8390f567ab69f296ed090e74c4dc9bcd16345c5e /target/arm/internals.h
parent4a16724f06ead684a5962477a557c26c677c2729 (diff)
target/arm: Clear exclusive monitor on v7M reset, exception entry/exit
For M profile we must clear the exclusive monitor on reset, exception entry and exception exit. We weren't doing any of these things; fix this bug. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1505137930-13255-3-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/internals.h')
-rw-r--r--target/arm/internals.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 5d7f24c95c..a315354cfd 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -444,6 +444,16 @@ void arm_handle_psci_call(ARMCPU *cpu);
#endif
/**
+ * arm_clear_exclusive: clear the exclusive monitor
+ * @env: CPU env
+ * Clear the CPU's exclusive monitor, like the guest CLREX instruction.
+ */
+static inline void arm_clear_exclusive(CPUARMState *env)
+{
+ env->exclusive_addr = -1;
+}
+
+/**
* ARMMMUFaultInfo: Information describing an ARM MMU Fault
* @s2addr: Address that caused a fault at stage 2
* @stage2: True if we faulted at stage 2