diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2018-10-08 14:55:03 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-10-08 14:55:03 +0100 |
| commit | 500d04843ba953dc4560e44f04001efec38c14a6 (patch) | |
| tree | 1fc9b3567ed9a7397f12277e50187d26fbdd9e91 /target/arm/internals.h | |
| parent | 116347ce20bb7b5cac17bf2b0e6f607530b50862 (diff) | |
target/arm: Pass TCGMemOpIdx to sve memory helpers
There is quite a lot of code required to compute cpu_mem_index,
or even put together the full TCGMemOpIdx. This can easily be
done at translation time.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181005175350.30752-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/internals.h')
| -rw-r--r-- | target/arm/internals.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/arm/internals.h b/target/arm/internals.h index dc9357766c..24c0444c8d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -796,4 +796,9 @@ static inline uint32_t arm_debug_exception_fsr(CPUARMState *env) } } +/* Note make_memop_idx reserves 4 bits for mmu_idx, and MO_BSWAP is bit 3. + * Thus a TCGMemOpIdx, without any MO_ALIGN bits, fits in 8 bits. + */ +#define MEMOPIDX_SHIFT 8 + #endif |