diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2017-07-27 11:59:08 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-07-31 13:09:52 +0100 |
| commit | 8531eb4f614a60e6582d4832b15eee09f7d27874 (patch) | |
| tree | 64f9633ddee4973ae9674cabafa7c6f3472091c9 /target/arm/helper.c | |
| parent | bf446a11dfb17ae7d8ed2b61a2444804eb458075 (diff) | |
target/arm: Rename cp15.c6_rgnr to pmsav7.rnr
Almost all of the PMSAv7 state is in the pmsav7 substruct of
the ARM CPU state structure. The exception is the region
number register, which is in cp15.c6_rgnr. This exception
is a bit odd for M profile, which otherwise generally does
not store state in the cp15 substruct.
Rename cp15.c6_rgnr to pmsav7.rnr accordingly.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1501153150-19984-4-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/helper.c')
| -rw-r--r-- | target/arm/helper.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index f0299c5282..0f79b25dc3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2385,7 +2385,7 @@ static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) return 0; } - u32p += env->cp15.c6_rgnr; + u32p += env->pmsav7.rnr; return *u32p; } @@ -2399,7 +2399,7 @@ static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, return; } - u32p += env->cp15.c6_rgnr; + u32p += env->pmsav7.rnr; tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ *u32p = value; } @@ -2447,7 +2447,7 @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] = { .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, .access = PL1_RW, - .fieldoffset = offsetof(CPUARMState, cp15.c6_rgnr), + .fieldoffset = offsetof(CPUARMState, pmsav7.rnr), .writefn = pmsav7_rgnr_write }, REGINFO_SENTINEL }; |