diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2018-01-25 11:45:29 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-01-25 11:45:29 +0000 |
| commit | 9a2b5256ea1f68c89d5da4b54f180f576c2c82d6 (patch) | |
| tree | 19c1c44a16c7fb249a2bfb1e23e06fe0794e699a /target/arm/helper.c | |
| parent | 3f68b8a5a6862f856524bb347bf348ae364dd43c (diff) | |
target/arm: Add aa{32, 64}_vfp_{dreg, qreg} helpers
Helpers that return a pointer into env->vfp.regs so that we isolate
the logic of how to index the regs array for different cpu modes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180119045438.28582-7-richard.henderson@linaro.org
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/helper.c')
| -rw-r--r-- | target/arm/helper.c | 32 |
1 files changed, 20 insertions, 12 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index ff5d78c4b8..a41b6c3a1b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -64,15 +64,16 @@ static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) /* VFP data registers are always little-endian. */ nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; if (reg < nregs) { - stq_le_p(buf, env->vfp.regs[reg]); + stq_le_p(buf, *aa32_vfp_dreg(env, reg)); return 8; } if (arm_feature(env, ARM_FEATURE_NEON)) { /* Aliases for Q regs. */ nregs += 16; if (reg < nregs) { - stq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); - stq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); + uint64_t *q = aa32_vfp_qreg(env, reg - 32); + stq_le_p(buf, q[0]); + stq_le_p(buf + 8, q[1]); return 16; } } @@ -90,14 +91,15 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; if (reg < nregs) { - env->vfp.regs[reg] = ldq_le_p(buf); + *aa32_vfp_dreg(env, reg) = ldq_le_p(buf); return 8; } if (arm_feature(env, ARM_FEATURE_NEON)) { nregs += 16; if (reg < nregs) { - env->vfp.regs[(reg - 32) * 2] = ldq_le_p(buf); - env->vfp.regs[(reg - 32) * 2 + 1] = ldq_le_p(buf + 8); + uint64_t *q = aa32_vfp_qreg(env, reg - 32); + q[0] = ldq_le_p(buf); + q[1] = ldq_le_p(buf + 8); return 16; } } @@ -114,9 +116,12 @@ static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) switch (reg) { case 0 ... 31: /* 128 bit FP register */ - stq_le_p(buf, env->vfp.regs[reg * 2]); - stq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]); - return 16; + { + uint64_t *q = aa64_vfp_qreg(env, reg); + stq_le_p(buf, q[0]); + stq_le_p(buf + 8, q[1]); + return 16; + } case 32: /* FPSR */ stl_p(buf, vfp_get_fpsr(env)); @@ -135,9 +140,12 @@ static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) switch (reg) { case 0 ... 31: /* 128 bit FP register */ - env->vfp.regs[reg * 2] = ldq_le_p(buf); - env->vfp.regs[reg * 2 + 1] = ldq_le_p(buf + 8); - return 16; + { + uint64_t *q = aa64_vfp_qreg(env, reg); + q[0] = ldq_le_p(buf); + q[1] = ldq_le_p(buf + 8); + return 16; + } case 32: /* FPSR */ vfp_set_fpsr(env, ldl_p(buf)); |