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authorPeter Maydell <peter.maydell@linaro.org>2017-09-14 18:43:17 +0100
committerPeter Maydell <peter.maydell@linaro.org>2017-09-14 18:43:17 +0100
commit4d1e7a4745c050f7ccac49a1c01437526b5130b5 (patch)
tree86add4663acf2e3d762a4d38790e5ac9a1cd43d7 /target/arm/helper.c
parent7115cdf5782922611bcc44c89eec5990db7f6466 (diff)
target/arm: Add and use defines for EXCRET constants
The exception-return magic values get some new bits in v8M, which makes some bit definitions for them worthwhile. We don't use the bit definitions for the switch on the low bits which checks the return type for v7M, because this is defined in the v7M ARM ARM as a set of valid values rather than via per-bit checks. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1505137930-13255-7-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/helper.c')
-rw-r--r--target/arm/helper.c14
1 files changed, 9 insertions, 5 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c
index fdd5cc6bae..a502e4eb33 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6242,7 +6242,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
" previous exception %d\n",
type, env->v7m.exception);
- if (extract32(type, 5, 23) != extract32(-1, 5, 23)) {
+ if ((type & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) {
qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception "
"exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", type);
}
@@ -6255,7 +6255,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
* which security state's faultmask to clear. (v8M ARM ARM R_KBNF.)
*/
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
- int es = type & 1;
+ int es = type & R_V7M_EXCRET_ES_MASK;
if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) {
env->v7m.faultmask[es] = 0;
}
@@ -6491,12 +6491,16 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
return; /* Never happens. Keep compiler happy. */
}
- lr = 0xfffffff1;
+ lr = R_V7M_EXCRET_RES1_MASK |
+ R_V7M_EXCRET_S_MASK |
+ R_V7M_EXCRET_DCRS_MASK |
+ R_V7M_EXCRET_FTYPE_MASK |
+ R_V7M_EXCRET_ES_MASK;
if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) {
- lr |= 4;
+ lr |= R_V7M_EXCRET_SPSEL_MASK;
}
if (!arm_v7m_is_handler_mode(env)) {
- lr |= 8;
+ lr |= R_V7M_EXCRET_MODE_MASK;
}
v7m_push_stack(cpu);