diff options
author | Peter Maydell <peter.maydell@linaro.org> | 2018-10-24 07:50:18 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2018-10-24 07:51:36 +0100 |
commit | eadb2febf05452bd8062c4c7823d7d789142500c (patch) | |
tree | 5863f36441121ee9ce5130a0c94f675b9a194ac4 /target/arm/helper.c | |
parent | 8a0fc3a29fc2315325400c738f807d0d4ae0ab7f (diff) |
target/arm: Implement HCR.PTW
If the HCR_EL2 PTW virtualizaiton configuration register bit
is set, then this means that a stage 2 Permission fault must
be generated if a stage 1 translation table access is made
to an address that is mapped as Device memory in stage 2.
Implement this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181012144235.19646-8-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/helper.c')
-rw-r--r-- | target/arm/helper.c | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 5017fd67e1..998c09aacb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9141,9 +9141,20 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, hwaddr s2pa; int s2prot; int ret; + ARMCacheAttrs cacheattrs = {}; + ARMCacheAttrs *pcacheattrs = NULL; + + if (env->cp15.hcr_el2 & HCR_PTW) { + /* + * PTW means we must fault if this S1 walk touches S2 Device + * memory; otherwise we don't care about the attributes and can + * save the S2 translation the effort of computing them. + */ + pcacheattrs = &cacheattrs; + } ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa, - &txattrs, &s2prot, &s2size, fi, NULL); + &txattrs, &s2prot, &s2size, fi, pcacheattrs); if (ret) { assert(fi->type != ARMFault_None); fi->s2addr = addr; @@ -9151,6 +9162,14 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, fi->s1ptw = true; return ~0; } + if (pcacheattrs && (pcacheattrs->attrs & 0xf0) == 0) { + /* Access was to Device memory: generate Permission fault */ + fi->type = ARMFault_Permission; + fi->s2addr = addr; + fi->stage2 = true; + fi->s1ptw = true; + return ~0; + } addr = s2pa; } return addr; |