diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2021-05-24 18:03:58 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-05-25 16:01:44 +0100 |
| commit | f8680aaa6e5bfc6022b75157c23db7d2ea98ab11 (patch) | |
| tree | e205a3fc166810e1c27b2b5a614a92c6e975d545 /target/arm/cpu_tcg.c | |
| parent | cdc8d8b273379a2842ad5cd220299352ea23065e (diff) | |
target/arm: Enable SVE2 and related extensions
Disable I8MM again for !have_neon during realize.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-93-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu_tcg.c')
| -rw-r--r-- | target/arm/cpu_tcg.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 046e476f65..d3458335ed 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -968,6 +968,7 @@ static void arm_max_initfn(Object *obj) t = FIELD_DP32(t, ID_ISAR6, FHM, 1); t = FIELD_DP32(t, ID_ISAR6, SB, 1); t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); + t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); cpu->isar.id_isar6 = t; t = cpu->isar.mvfr1; |