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| author | Richard Henderson <richard.henderson@linaro.org> | 2019-03-01 12:04:57 -0800 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-03-05 15:55:08 +0000 |
| commit | 2fba34f70d9a81bab56e61bb99a4d6632bdfe531 (patch) | |
| tree | 4a8c458fca25a67e2bab86fd93d19c8a40939fa7 /target/arm/cpu64.c | |
| parent | 22ac3c49641f6eed93dca5b852030b4d3eacf6c4 (diff) | |
target/arm: Rearrange disas_data_proc_reg
This decoding more closely matches the ARMv8.4 Table C4-6,
Encoding table for Data Processing - Register Group.
In particular, op2 == 0 is now more than just Add/sub (with carry).
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190301200501.16533-7-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu64.c')
0 files changed, 0 insertions, 0 deletions