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authorRichard Henderson <richard.henderson@linaro.org>2023-02-27 11:33:29 -1000
committerPeter Maydell <peter.maydell@linaro.org>2023-03-06 14:08:12 +0000
commit7d8b28b8b5d9d1b68d27b4f5a0329d114b5ce2ee (patch)
tree1be2db9c8596958b21462ce0592462650a868236 /target/arm/cpu.h
parent6c8676512f347cc6c3d89bed45540df08fb2b4ef (diff)
target/arm: Implement gdbstub m-profile systemreg and secext
The upstream gdb xml only implements {MSP,PSP}{,_NS,S}, but go ahead and implement the other system registers as well. Since there is significant overlap between the two, implement them with common code. The only exception is the systemreg view of CONTROL, which merges the banked bits as per MRS. Signed-off-by: David Reiss <dreiss@meta.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230227213329.793795-15-richard.henderson@linaro.org [rth: Substatial rewrite using enumerator and shared code.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
-rw-r--r--target/arm/cpu.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 379e74d1f9..c4bd22808c 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -869,6 +869,8 @@ struct ArchCPU {
DynamicGDBXMLInfo dyn_sysreg_xml;
DynamicGDBXMLInfo dyn_svereg_xml;
+ DynamicGDBXMLInfo dyn_m_systemreg_xml;
+ DynamicGDBXMLInfo dyn_m_secextreg_xml;
/* Timers used by the generic (architected) timer */
QEMUTimer *gt_timer[NUM_GTIMERS];