diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2019-02-01 16:39:17 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-02-01 16:39:17 +0000 |
| commit | e83d74286cad2b9b967e1ba0ce5c8d16cba9679f (patch) | |
| tree | bd57034a1550568ec8f9d6aa4457fd38531e9c17 /target/arm/cpu.h | |
| parent | a1bc3e7dc8f89facee6d3c25fb8465f8feccef1f (diff) | |
| parent | 7743b70ffe7a8ce168adce2cf50ad156b1fefb8c (diff) | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190201' into staging
target-arm queue:
* New machine mps2-an521 -- this is a model of the AN521 FPGA image for the MPS2 devboard
* Fix various places where we failed to UNDEF invalid A64 instructions
* Don't UNDEF a valid FCMLA on 32-bit inputs
* Fix some bugs in the newly-added PAuth implementation
* microbit: Implement NVMC non-volatile memory controller
# gpg: Signature made Fri 01 Feb 2019 16:06:03 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20190201: (47 commits)
tests/microbit-test: Add tests for nRF51 NVMC
arm: Instantiate NRF51 special NVM's and NVMC
hw/nvram/nrf51_nvm: Add nRF51 non-volatile memories
target/arm: fix decoding of B{,L}RA{A,B}
target/arm: fix AArch64 virtual address space size
linux-user: Initialize aarch64 pac keys
aarch64-linux-user: Enable HWCAP bits for PAuth
aarch64-linux-user: Update HWCAP bits from linux 5.0-rc1
target/arm: Always enable pac keys for user-only
arm: Clarify the logic of set_pc()
target/arm: Enable API, APK bits in SCR, HCR
target/arm: Add a timer to predict PMU counter overflow
target/arm: Send interrupts on PMU counter overflow
target/arm/translate-a64: Fix mishandling of size in FCMLA decode
target/arm/translate-a64: Fix FCMLA decoding error
exec.c: Don't reallocate IOMMUNotifiers that are in use
target/arm/translate-a64: Don't underdecode SDOT and UDOT
target/arm/translate-a64: Don't underdecode FP insns
target/arm/translate-a64: Don't underdecode add/sub extended register
target/arm/translate-a64: Don't underdecode SIMD ld/st single
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b8161cb6d7..a68bcc9fed 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -746,6 +746,11 @@ struct ARMCPU { /* Timers used by the generic (architected) timer */ QEMUTimer *gt_timer[NUM_GTIMERS]; + /* + * Timer used by the PMU. Its state is restored after migration by + * pmu_op_finish() - it does not need other handling during migration + */ + QEMUTimer *pmu_timer; /* GPIO outputs for generic timer */ qemu_irq gt_timer_outputs[NUM_GTIMERS]; /* GPIO output for GICv3 maintenance interrupt signal */ @@ -1005,6 +1010,11 @@ void pmccntr_op_finish(CPUARMState *env); void pmu_op_start(CPUARMState *env); void pmu_op_finish(CPUARMState *env); +/* + * Called when a PMU counter is due to overflow + */ +void arm_pmu_timer_cb(void *opaque); + /** * Functions to register as EL change hooks for PMU mode filtering */ @@ -2502,7 +2512,7 @@ bool write_cpustate_to_list(ARMCPU *cpu); #if defined(TARGET_AARCH64) # define TARGET_PHYS_ADDR_SPACE_BITS 48 -# define TARGET_VIRT_ADDR_SPACE_BITS 64 +# define TARGET_VIRT_ADDR_SPACE_BITS 48 #else # define TARGET_PHYS_ADDR_SPACE_BITS 40 # define TARGET_VIRT_ADDR_SPACE_BITS 32 |