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authorPeter Maydell <peter.maydell@linaro.org>2017-10-06 16:46:48 +0100
committerPeter Maydell <peter.maydell@linaro.org>2017-10-06 16:46:48 +0100
commitbed079da04dd9e0e249b9bc22bca8dce58b67f40 (patch)
tree4055d1e6a764ac79b96e9598b8e8e10d66261099 /target/arm/cpu.h
parent4e4259d3c574a8e89c3af27bcb84bc19a442efb1 (diff)
target/arm: Add new-in-v8M SFSR and SFAR
Add the new M profile Secure Fault Status Register and Secure Fault Address Register. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1506092407-26985-10-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
-rw-r--r--target/arm/cpu.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ad6eff498b..9e3a16dad5 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -443,8 +443,10 @@ typedef struct CPUARMState {
uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */
uint32_t hfsr; /* HardFault Status */
uint32_t dfsr; /* Debug Fault Status Register */
+ uint32_t sfsr; /* Secure Fault Status Register */
uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */
uint32_t bfar; /* BusFault Address */
+ uint32_t sfar; /* Secure Fault Address Register */
unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */
int exception;
uint32_t primask[M_REG_NUM_BANKS];
@@ -1260,6 +1262,16 @@ FIELD(V7M_DFSR, DWTTRAP, 2, 1)
FIELD(V7M_DFSR, VCATCH, 3, 1)
FIELD(V7M_DFSR, EXTERNAL, 4, 1)
+/* V7M SFSR bits */
+FIELD(V7M_SFSR, INVEP, 0, 1)
+FIELD(V7M_SFSR, INVIS, 1, 1)
+FIELD(V7M_SFSR, INVER, 2, 1)
+FIELD(V7M_SFSR, AUVIOL, 3, 1)
+FIELD(V7M_SFSR, INVTRAN, 4, 1)
+FIELD(V7M_SFSR, LSPERR, 5, 1)
+FIELD(V7M_SFSR, SFARVALID, 6, 1)
+FIELD(V7M_SFSR, LSERR, 7, 1)
+
/* v7M MPU_CTRL bits */
FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)