diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2018-12-13 13:48:07 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-12-13 14:41:24 +0000 |
| commit | ab638a328fd099ba0b23c8c818eb39f2c35414f3 (patch) | |
| tree | 71b08a787a56dccce839f68b9e6fd70951070671 /target/arm/cpu.h | |
| parent | 037c13c5904f5fc67bb0ab7dd91ae07347aedee9 (diff) | |
target/arm: Implement the ARMv8.2-AA32HPD extension
The bulk of the work here, beyond base HPD, is defining the
TTBCR2 register. In addition we must check TTBCR.T2E, which
is not present (RES0) for AArch64.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181203203839.757-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b8dbdb5e01..11ec2cce76 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1548,6 +1548,15 @@ FIELD(ID_ISAR6, FHM, 8, 4) FIELD(ID_ISAR6, SB, 12, 4) FIELD(ID_ISAR6, SPECRES, 16, 4) +FIELD(ID_MMFR4, SPECSEI, 0, 4) +FIELD(ID_MMFR4, AC2, 4, 4) +FIELD(ID_MMFR4, XNX, 8, 4) +FIELD(ID_MMFR4, CNP, 12, 4) +FIELD(ID_MMFR4, HPDS, 16, 4) +FIELD(ID_MMFR4, LSM, 20, 4) +FIELD(ID_MMFR4, CCIDX, 24, 4) +FIELD(ID_MMFR4, EVT, 28, 4) + FIELD(ID_AA64ISAR0, AES, 4, 4) FIELD(ID_AA64ISAR0, SHA1, 8, 4) FIELD(ID_AA64ISAR0, SHA2, 12, 4) |