diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2018-02-15 18:29:37 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-02-15 18:29:49 +0000 |
| commit | 24ac0fb129f9ce9dd96901b2377fc6271dc55b2b (patch) | |
| tree | 46dc892a0c6393c7fb38691d96c3b3ebd06fd08a /target/arm/cpu.h | |
| parent | 43bbce7fbef22adf687dd84934fd0b2f8df807a8 (diff) | |
hw/intc/armv7m_nvic: Implement SCR
We were previously making the system control register (SCR)
just RAZ/WI. Although we don't implement the functionality
this register controls, we should at least provide the state,
including the banked state for v8M.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180209165810.6668-7-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8938a7c953..bc0638d3fa 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -497,6 +497,7 @@ typedef struct CPUARMState { uint32_t aircr; /* only holds r/w state if security extn implemented */ uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ uint32_t csselr[M_REG_NUM_BANKS]; + uint32_t scr[M_REG_NUM_BANKS]; } v7m; /* Information associated with an exception about to be taken: @@ -1258,6 +1259,12 @@ FIELD(V7M_CCR, STKALIGN, 9, 1) FIELD(V7M_CCR, DC, 16, 1) FIELD(V7M_CCR, IC, 17, 1) +/* V7M SCR bits */ +FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) +FIELD(V7M_SCR, SLEEPDEEP, 2, 1) +FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) +FIELD(V7M_SCR, SEVONPEND, 4, 1) + /* V7M AIRCR bits */ FIELD(V7M_AIRCR, VECTRESET, 0, 1) FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) |