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authorRichard Henderson <richard.henderson@linaro.org>2018-12-13 13:48:05 +0000
committerPeter Maydell <peter.maydell@linaro.org>2018-12-13 14:41:24 +0000
commitea22747c63c9a894777aa41a7af85c3d08e39f81 (patch)
tree8c6e6e23add6b8a95f2aed79e6e3c198443d0b09 /target/arm/cpu.h
parent619959c3583dad325c36f09ce670e7d091382cae (diff)
target/arm: Tidy scr_write
Because EL3 has a fixed execution mode, we can properly decide which of the bits are RES{0,1}. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181203203839.757-8-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
-rw-r--r--target/arm/cpu.h2
1 files changed, 0 insertions, 2 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 20d97b66de..b8dbdb5e01 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1312,8 +1312,6 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
#define SCR_FIEN (1U << 21)
#define SCR_ENSCXT (1U << 25)
#define SCR_ATA (1U << 26)
-#define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
-#define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
/* Return the current FPSCR value. */
uint32_t vfp_get_fpscr(CPUARMState *env);