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authorPeter Maydell <peter.maydell@linaro.org>2019-04-29 17:36:01 +0100
committerPeter Maydell <peter.maydell@linaro.org>2019-04-29 17:36:01 +0100
commitea7ac69d124c94c6e5579145e727adec9ccbefef (patch)
treebbfab88c96e2aca57c559f5c0a19797d0f8f919c /target/arm/cpu.c
parent7fbb535f7aeb22896fedfcf18a1eeff48165f1d7 (diff)
target/arm: Overlap VECSTRIDE and XSCALE_CPAR TB flags
We are close to running out of TB flags for AArch32; we could start using the cs_base word, but before we do that we can economise on our usage by sharing the same bits for the VFP VECSTRIDE field and the XScale XSCALE_CPAR field. This works because no XScale CPU ever had VFP. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190416125744.27770-18-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.c')
-rw-r--r--target/arm/cpu.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index be81e197ee..7deccda240 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1034,6 +1034,13 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
set_feature(env, ARM_FEATURE_THUMB_DSP);
}
+ /*
+ * We rely on no XScale CPU having VFP so we can use the same bits in the
+ * TB flags field for VECSTRIDE and XSCALE_CPAR.
+ */
+ assert(!(arm_feature(env, ARM_FEATURE_VFP) &&
+ arm_feature(env, ARM_FEATURE_XSCALE)));
+
if (arm_feature(env, ARM_FEATURE_V7) &&
!arm_feature(env, ARM_FEATURE_M) &&
!arm_feature(env, ARM_FEATURE_PMSA)) {