diff options
| author | Alex Bennée <alex.bennee@linaro.org> | 2020-03-16 17:21:44 +0000 |
|---|---|---|
| committer | Alex Bennée <alex.bennee@linaro.org> | 2020-03-17 17:38:38 +0000 |
| commit | 7b6a2198e71794c851f39ac7a92d39692c786820 (patch) | |
| tree | 7915f2acf2335f84c7c09aa7a0211ea95d7b6478 /target/arm/cpu.c | |
| parent | 32d6e32afa694ebedf2c5f3bf6f013c5debb5959 (diff) | |
target/arm: default SVE length to 64 bytes for linux-user
The Linux kernel chooses the default of 64 bytes for SVE registers on
the basis that it is the largest size on known hardware that won't
grow the signal frame. We still honour the sve-max-vq property and
userspace can expand the number of lanes by calling PR_SVE_SET_VL.
This should not make any difference to SVE enabled software as the SVE
is of course vector length agnostic.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200316172155.971-18-alex.bennee@linaro.org>
Diffstat (limited to 'target/arm/cpu.c')
| -rw-r--r-- | target/arm/cpu.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3623ecefbd..0909ce86a1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -195,9 +195,10 @@ static void arm_cpu_reset(CPUState *s) env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); /* and to the SVE instructions */ env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); - /* with maximum vector length */ - env->vfp.zcr_el[1] = cpu_isar_feature(aa64_sve, cpu) ? - cpu->sve_max_vq - 1 : 0; + /* with reasonable vector length */ + if (cpu_isar_feature(aa64_sve, cpu)) { + env->vfp.zcr_el[1] = MIN(cpu->sve_max_vq - 1, 3); + } /* * Enable TBI0 and TBI1. While the real kernel only enables TBI0, * turning on both here will produce smaller code and otherwise |