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authorRichard Henderson <richard.henderson@linaro.org>2023-06-23 11:15:43 +0100
committerPeter Maydell <peter.maydell@linaro.org>2023-06-23 11:15:43 +0100
commitb9f335c24705883391ea52035c9b2229e6992eee (patch)
tree055483f615b74e622cfe6d3a86cd960635afe7cc /target/arm/cpu.c
parentb455ce4c2f300c8ba47cba7232dd03261368a4cb (diff)
target/arm: Add isar_feature_aa64_rme
Add the missing field for ID_AA64PFR0, and the predicate. Disable it if EL3 is forced off by the board or command-line. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230620124418.805717-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.c')
-rw-r--r--target/arm/cpu.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 353fc48567..842e1b53ee 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1989,6 +1989,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
ID_AA64PFR0, EL3, 0);
+
+ /* Disable the realm management extension, which requires EL3. */
+ cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
+ ID_AA64PFR0, RME, 0);
}
if (!cpu->has_el2) {