diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2022-07-08 20:45:38 +0530 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-07-11 13:43:52 +0100 |
| commit | 4630353559fc1924c5f692aacb0d52e7e9ba5f5c (patch) | |
| tree | 386990281e949187627924b8322978eb525ffe5a /target/arm/cpu.c | |
| parent | 24d87c187c46a935f2b6bd7194d9958fb28be786 (diff) | |
target/arm: Only set ZEN in reset if SVE present
There's no reason to set CPACR_EL1.ZEN if SVE disabled.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-44-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.c')
| -rw-r--r-- | target/arm/cpu.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9c58be8b14..9b54443843 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -204,11 +204,10 @@ static void arm_cpu_reset(DeviceState *dev) /* and to the FP/Neon instructions */ env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, CPACR_EL1, FPEN, 3); - /* and to the SVE instructions */ - env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, - CPACR_EL1, ZEN, 3); - /* with reasonable vector length */ + /* and to the SVE instructions, with default vector length */ if (cpu_isar_feature(aa64_sve, cpu)) { + env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, + CPACR_EL1, ZEN, 3); env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; } /* |