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authorJulia Suvorova <jusual@mail.ru>2018-08-14 17:17:19 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-08-14 17:17:19 +0100
commit22ab3460017cfcfb6b50f05838ad142e08becce5 (patch)
tree785a9721a6e4a75b6878ded40e11d886b399de05 /target/arm/cpu.c
parent7c9140afd594d7be73320ffaeb08210c59eaf168 (diff)
arm: Add ARMv6-M programmer's model support
Forbid stack alignment change. (CCR) Reserve FAULTMASK, BASEPRI registers. Report any fault as a HardFault. Disable MemManage, BusFault and UsageFault, so they always escalated to HardFault. (SHCSR) Signed-off-by: Julia Suvorova <jusual@mail.ru> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20180718095628.26442-1-jusual@mail.ru Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.c')
-rw-r--r--target/arm/cpu.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 64a8005a4b..3848ef46aa 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -231,6 +231,10 @@ static void arm_cpu_reset(CPUState *s)
env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK;
env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK;
}
+ if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
+ env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK;
+ env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
+ }
/* Unlike A/R profile, M profile defines the reset LR value */
env->regs[14] = 0xffffffff;