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authorAurelien Jarno <aurelien@aurel32.net>2012-10-01 21:00:42 +0200
committerAurelien Jarno <aurelien@aurel32.net>2012-10-06 12:22:29 +0200
commitf783cb22409c6537b3cab7e78e527f62b4237d1e (patch)
treec68043f67cd002516134da347d7be6ea50f53ccc /target-xtensa
parentc9159fe9aa9abe24115ea4d16127179e9cb07e22 (diff)
target-xtensa: de-optimize EXTUI
Now that "and" with 0xff, 0xffff and 0xffffffff and "shr" with 0 shift are optimized in tcg/tcg-op.h there is no need to do it in target-xtensa/translate.c. Acked-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-xtensa')
-rw-r--r--target-xtensa/translate.c22
1 files changed, 2 insertions, 20 deletions
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index b9acd706ce..82e8cccadc 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -1829,26 +1829,8 @@ static void disas_xtensa_insn(DisasContext *dc)
int maskimm = (1 << (OP2 + 1)) - 1;
TCGv_i32 tmp = tcg_temp_new_i32();
-
- if (shiftimm) {
- tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
- } else {
- tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
- }
-
- switch (maskimm) {
- case 0xff:
- tcg_gen_ext8u_i32(cpu_R[RRR_R], tmp);
- break;
-
- case 0xffff:
- tcg_gen_ext16u_i32(cpu_R[RRR_R], tmp);
- break;
-
- default:
- tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
- break;
- }
+ tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
+ tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
tcg_temp_free(tmp);
}
break;