diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2015-10-21 21:21:29 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-10-21 21:21:29 +0100 |
| commit | c1bd8997438f1b556acfeab1d52245ff7cc680c0 (patch) | |
| tree | 97058af758983de0f2df5190105d1f1b637d4229 /target-xtensa/translate.c | |
| parent | 8bfaa25fce2c22060a17501980943538801056de (diff) | |
| parent | 19b7bec4a37b081ed326293148fd793f04896b59 (diff) | |
Merge remote-tracking branch 'remotes/xtensa/tags/20151021-xtensa' into staging
Xtensa updates:
- fix register window overflow with l32e/s32e instructions;
- make MMU events logging dependent on CPU_LOG_MMU;
- attach FLASH to system I/O region on XTFPGA boards;
- implement depbits and l32nb instructions.
# gpg: Signature made Wed 21 Oct 2015 19:34:02 BST using RSA key ID F83FA044
# gpg: Good signature from "Max Filippov <max.filippov@cogentembedded.com>"
# gpg: aka "Max Filippov <jcmvbkbc@gmail.com>"
* remotes/xtensa/tags/20151021-xtensa:
target-xtensa: implement S32NB
target-xtensa: implement depbits instruction
target-xtensa: xtfpga: attach FLASH to system IO
target-xtensa: use CPU_LOG_MMU for MMU event logging
target-xtensa: add window overflow check to L32E/S32E
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-xtensa/translate.c')
| -rw-r--r-- | target-xtensa/translate.c | 37 |
1 files changed, 35 insertions, 2 deletions
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index fda91b7e5d..aa0c527dc4 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -1943,7 +1943,8 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) switch (OP2) { case 0: /*L32E*/ HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); - if (gen_check_privilege(dc)) { + if (gen_check_privilege(dc) && + gen_window_check2(dc, RRR_S, RRR_T)) { TCGv_i32 addr = tcg_temp_new_i32(); tcg_gen_addi_i32(addr, cpu_R[RRR_S], (0xffffffc0 | (RRR_R << 2))); @@ -1954,7 +1955,8 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) case 4: /*S32E*/ HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); - if (gen_check_privilege(dc)) { + if (gen_check_privilege(dc) && + gen_window_check2(dc, RRR_S, RRR_T)) { TCGv_i32 addr = tcg_temp_new_i32(); tcg_gen_addi_i32(addr, cpu_R[RRR_S], (0xffffffc0 | (RRR_R << 2))); @@ -1963,6 +1965,17 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) } break; + case 5: /*S32N*/ + if (gen_window_check2(dc, RRI4_S, RRI4_T)) { + TCGv_i32 addr = tcg_temp_new_i32(); + + tcg_gen_addi_i32(addr, cpu_R[RRI4_S], RRI4_IMM4 << 2); + gen_load_store_alignment(dc, 2, addr, false); + tcg_gen_qemu_st32(cpu_R[RRI4_T], addr, dc->cring); + tcg_temp_free(addr); + } + break; + default: RESERVED(); break; @@ -1970,6 +1983,16 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) break; case 10: /*FP0*/ + /*DEPBITS*/ + if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) { + if (!gen_window_check2(dc, RRR_S, RRR_T)) { + break; + } + tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S], + OP2, RRR_R + 1); + break; + } + HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); switch (OP2) { case 0: /*ADD.Sf*/ @@ -2104,6 +2127,16 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) break; case 11: /*FP1*/ + /*DEPBITS*/ + if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) { + if (!gen_window_check2(dc, RRR_S, RRR_T)) { + break; + } + tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S], + OP2 + 16, RRR_R + 1); + break; + } + HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); #define gen_compare(rel, br, a, b) \ |