diff options
| author | Max Filippov <jcmvbkbc@gmail.com> | 2012-04-10 02:48:18 +0400 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-04-14 15:25:38 +0000 |
| commit | 3d0be8a5c135dadcfbd68ed354007a8cece98849 (patch) | |
| tree | f8d2524bd5d5fa16623ce5aed68783542904c810 /target-xtensa/translate.c | |
| parent | 1e7855a558085d6acd0aba4e3278b594d05df1ec (diff) | |
target-xtensa: fix tb invalidation for IBREAK and LOOP
Instruction breakpoint/zero overhead loop handling code is built into
TBs pointed to by IBREAKA/LEND SRs. When these or related SRs get
changed TBs at virtual addresses corresponding to their old and their
new values must be invalidated.
Virtual address range is passed to the tb_invalidate_phys_page_range,
which is incorrect in system emulation mode.
To fix it use guest TLB/MMU to translate virtual address to physical
address.
However the guest may not have virtual-to-physical mapping at the moment
of IBREAKA/LEND change, thus this fix is not 100% accurate.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-xtensa/translate.c')
| -rw-r--r-- | target-xtensa/translate.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 492dbccd53..6900123983 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -459,11 +459,13 @@ static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr) static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s) { gen_helper_wsr_lbeg(s); + gen_jumpi_check_loop_end(dc, 0); } static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s) { gen_helper_wsr_lend(s); + gen_jumpi_check_loop_end(dc, 0); } static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s) |