diff options
| author | Max Filippov <jcmvbkbc@gmail.com> | 2012-12-05 07:15:21 +0400 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-12-08 18:48:26 +0000 |
| commit | 4e41d2f5830a76d3fe92b3d3b18cc9f2ee927770 (patch) | |
| tree | 60e3cc172d4aa177b460d5e72b176a8bd3c95915 /target-xtensa/translate.c | |
| parent | fcc803d119a4c01a9b0ee5bda35fda1eeabffa33 (diff) | |
target-xtensa: implement CACHEATTR SR
In XEA1, the Options for Memory Protection and Translation and the
corresponding TLB management instructions are not available. Instead,
functionality similar to the Region Protection Option is available
through the cache attribute register. See ISA, A.2.14 for details.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-xtensa/translate.c')
| -rw-r--r-- | target-xtensa/translate.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index dc08de51ba..eb4812099e 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -99,6 +99,7 @@ static const char * const sregnames[256] = { [ITLBCFG] = "ITLBCFG", [DTLBCFG] = "DTLBCFG", [IBREAKENABLE] = "IBREAKENABLE", + [CACHEATTR] = "CACHEATTR", [ATOMCTL] = "ATOMCTL", [IBREAKA] = "IBREAKA0", [IBREAKA + 1] = "IBREAKA1", |