diff options
| author | Max Filippov <jcmvbkbc@gmail.com> | 2012-09-21 02:59:49 +0400 |
|---|---|---|
| committer | malc <av1474@comtv.ru> | 2012-09-21 03:07:27 +0400 |
| commit | f9cb5045d1eb6d187b0849d0f36735d3aac1a37f (patch) | |
| tree | 0d4e99397706771f4229873d2f0123c687b62dad /target-xtensa/translate.c | |
| parent | a25506603914d706f4ac4c63d3b93b4f1227b9b4 (diff) | |
target-xtensa: fix extui shift amount
extui opcode only uses lowermost op1 bit for sa4.
Reported-by: malc <av1474@comtv.ru>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: malc <av1474@comtv.ru>
Diffstat (limited to 'target-xtensa/translate.c')
| -rw-r--r-- | target-xtensa/translate.c | 24 |
1 files changed, 21 insertions, 3 deletions
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 1900bd5d44..7a1c528fc8 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -1778,12 +1778,30 @@ static void disas_xtensa_insn(DisasContext *dc) case 5: gen_window_check2(dc, RRR_R, RRR_T); { - int shiftimm = RRR_S | (OP1 << 4); + int shiftimm = RRR_S | ((OP1 & 1) << 4); int maskimm = (1 << (OP2 + 1)) - 1; TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm); - tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm); + + if (shiftimm) { + tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm); + } else { + tcg_gen_mov_i32(tmp, cpu_R[RRR_T]); + } + + switch (maskimm) { + case 0xff: + tcg_gen_ext8u_i32(cpu_R[RRR_R], tmp); + break; + + case 0xffff: + tcg_gen_ext16u_i32(cpu_R[RRR_R], tmp); + break; + + default: + tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm); + break; + } tcg_temp_free(tmp); } break; |