diff options
| author | Richard Henderson <rth@twiddle.net> | 2013-02-19 23:52:25 -0800 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2013-02-23 17:25:31 +0000 |
| commit | c9cda20bc55e549d31e791bfa55eabe3642b73a7 (patch) | |
| tree | 9b7eac0e82be53c8fce9a6c6081067e574c17305 /target-xtensa/translate.c | |
| parent | d1f8cd839136337b713a05aaf11a5f189e81532d (diff) | |
target-xtensa: Use mul*2 for mul*hi
Cc: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-xtensa/translate.c')
| -rw-r--r-- | target-xtensa/translate.c | 20 |
1 files changed, 6 insertions, 14 deletions
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 7029ac4814..b41d12c540 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -1652,24 +1652,16 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) case 11: /*MULSHi*/ HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH); { - TCGv_i64 r = tcg_temp_new_i64(); - TCGv_i64 s = tcg_temp_new_i64(); - TCGv_i64 t = tcg_temp_new_i64(); + TCGv lo = tcg_temp_new(); if (OP2 == 10) { - tcg_gen_extu_i32_i64(s, cpu_R[RRR_S]); - tcg_gen_extu_i32_i64(t, cpu_R[RRR_T]); + tcg_gen_mulu2_i32(lo, cpu_R[RRR_R], + cpu_R[RRR_S], cpu_R[RRR_T]); } else { - tcg_gen_ext_i32_i64(s, cpu_R[RRR_S]); - tcg_gen_ext_i32_i64(t, cpu_R[RRR_T]); + tcg_gen_muls2_i32(lo, cpu_R[RRR_R], + cpu_R[RRR_S], cpu_R[RRR_T]); } - tcg_gen_mul_i64(r, s, t); - tcg_gen_shri_i64(r, r, 32); - tcg_gen_trunc_i64_i32(cpu_R[RRR_R], r); - - tcg_temp_free_i64(r); - tcg_temp_free_i64(s); - tcg_temp_free_i64(t); + tcg_temp_free(lo); } break; |