diff options
| author | Max Filippov <jcmvbkbc@gmail.com> | 2015-07-12 02:10:17 +0300 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2015-10-21 21:29:25 +0300 |
| commit | 5eeb40c5b1f00c4ee4fcf2f33087697d7ba6f5f6 (patch) | |
| tree | 905608e83c2d6180f862d13cec353016691725b0 /target-xtensa/translate.c | |
| parent | 68931a4082812f56657b39168e815c48f0ab0a8c (diff) | |
target-xtensa: implement depbits instruction
This option provides an instruction for depositing a bit field from the
least significant position of one register to an arbitrary position in
another register.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target-xtensa/translate.c')
| -rw-r--r-- | target-xtensa/translate.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 1349d2f3da..be5eb25627 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -1972,6 +1972,16 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) break; case 10: /*FP0*/ + /*DEPBITS*/ + if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) { + if (!gen_window_check2(dc, RRR_S, RRR_T)) { + break; + } + tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S], + OP2, RRR_R + 1); + break; + } + HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); switch (OP2) { case 0: /*ADD.Sf*/ @@ -2106,6 +2116,16 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) break; case 11: /*FP1*/ + /*DEPBITS*/ + if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) { + if (!gen_window_check2(dc, RRR_S, RRR_T)) { + break; + } + tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S], + OP2 + 16, RRR_R + 1); + break; + } + HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); #define gen_compare(rel, br, a, b) \ |