diff options
| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2014-12-03 17:40:21 +0000 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2014-12-21 18:35:38 +0000 |
| commit | 436d63ff3e3f87cda3e8df35827a40093cc17430 (patch) | |
| tree | 62ecb383161ebf03bd775288046fb30836269aa0 /target-tricore | |
| parent | b5fd8fa34594da327e2965a8c3b5dddf21f862ff (diff) | |
target-tricore: Fix MFCR/MTCR insn and B format offset.
Fix gen_mtcr using wrong register.
Fix gen_mtcr/mfcr using sign extended offsets.
Fix B format insn using not sign extendend offsets.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-tricore')
| -rw-r--r-- | target-tricore/translate.c | 6 | ||||
| -rw-r--r-- | target-tricore/tricore-opcodes.h | 2 |
2 files changed, 6 insertions, 2 deletions
diff --git a/target-tricore/translate.c b/target-tricore/translate.c index ecb2399ccd..bd35c299cf 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -3939,6 +3939,7 @@ static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx, tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16); break; case OPC1_32_RLC_MFCR: + const16 = MASK_OP_RLC_CONST16(ctx->opcode); gen_mfcr(env, cpu_gpr_d[r2], const16); break; case OPC1_32_RLC_MOV: @@ -3966,7 +3967,8 @@ static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx, tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16); break; case OPC1_32_RLC_MTCR: - gen_mtcr(env, ctx, cpu_gpr_d[r2], const16); + const16 = MASK_OP_RLC_CONST16(ctx->opcode); + gen_mtcr(env, ctx, cpu_gpr_d[r1], const16); break; } } @@ -4670,7 +4672,7 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) case OPC1_32_B_JA: case OPC1_32_B_JL: case OPC1_32_B_JLA: - address = MASK_OP_B_DISP24(ctx->opcode); + address = MASK_OP_B_DISP24_SEXT(ctx->opcode); gen_compute_branch(ctx, op1, 0, 0, 0, address); break; /* Bit-format */ diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index afc22883e0..919063e422 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -94,6 +94,8 @@ /* B Format */ #define MASK_OP_B_DISP24(op) (MASK_BITS_SHIFT(op, 16, 31) + \ (MASK_BITS_SHIFT(op, 8, 15) << 16)) +#define MASK_OP_B_DISP24_SEXT(op) (MASK_BITS_SHIFT(op, 16, 31) + \ + (MASK_BITS_SHIFT_SEXT(op, 8, 15) << 16)) /* BIT Format */ #define MASK_OP_BIT_D(op) MASK_BITS_SHIFT(op, 28, 31) #define MASK_OP_BIT_POS2(op) MASK_BITS_SHIFT(op, 23, 27) |