diff options
| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2015-05-07 19:55:37 +0200 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2015-05-22 17:02:33 +0200 |
| commit | e5c96c82bc529674b61eacd221734abc2674e264 (patch) | |
| tree | 1f868a6fbb25d9bf931752028c2afdac97cb4d8c /target-tricore | |
| parent | ddd8cebe3106bdfb2681d8d283296199fd6c7417 (diff) | |
target-tricore: add RR_CRC32 instruction of the v1.6.1 ISA
This instruction was introduced by the new Aurix platform.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-tricore')
| -rw-r--r-- | target-tricore/helper.h | 2 | ||||
| -rw-r--r-- | target-tricore/op_helper.c | 11 | ||||
| -rw-r--r-- | target-tricore/translate.c | 5 | ||||
| -rw-r--r-- | target-tricore/tricore-opcodes.h | 1 |
4 files changed, 19 insertions, 0 deletions
diff --git a/target-tricore/helper.h b/target-tricore/helper.h index 1a49b00ccb..842506c5f9 100644 --- a/target-tricore/helper.h +++ b/target-tricore/helper.h @@ -117,6 +117,8 @@ DEF_HELPER_FLAGS_2(dvstep_u, TCG_CALL_NO_RWG_SE, i64, i64, i32) DEF_HELPER_FLAGS_5(mul_h, TCG_CALL_NO_RWG_SE, i64, i32, i32, i32, i32, i32) DEF_HELPER_FLAGS_5(mulm_h, TCG_CALL_NO_RWG_SE, i64, i32, i32, i32, i32, i32) DEF_HELPER_FLAGS_5(mulr_h, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32, i32, i32) +/* crc32 */ +DEF_HELPER_FLAGS_2(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32) /* CSA */ DEF_HELPER_2(call, void, env, i32) DEF_HELPER_1(ret, void, env) diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c index 9919b5b17b..7aa1f8e40e 100644 --- a/target-tricore/op_helper.c +++ b/target-tricore/op_helper.c @@ -19,6 +19,7 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" +#include <zlib.h> /* for crc32 */ /* Addressing mode helper */ @@ -2165,6 +2166,16 @@ uint32_t helper_mulr_h(uint32_t arg00, uint32_t arg01, return (result1 & 0xffff0000) | (result0 >> 16); } +uint32_t helper_crc32(uint32_t arg0, uint32_t arg1) +{ + uint8_t buf[4]; + uint32_t ret; + stl_be_p(buf, arg0); + + ret = crc32(arg1, buf, 4); + return ret; +} + /* context save area (CSA) related helpers */ static int cdc_increment(target_ulong *psw) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index b2e25e7c7f..52f474ba9f 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -6449,6 +6449,11 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) case OPC2_32_RR_UNPACK: gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); break; + case OPC2_32_RR_CRC32: + if (tricore_feature(env, TRICORE_FEATURE_161)) { + gen_helper_crc32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); + } /* TODO: else raise illegal opcode trap */ + break; } } diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index 7ad6df9bd6..440c7fefed 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -1120,6 +1120,7 @@ enum { OPC2_32_RR_DVINIT_U = 0x0a, OPC2_32_RR_PARITY = 0x02, OPC2_32_RR_UNPACK = 0x08, + OPC2_32_RR_CRC32 = 0x03, }; /* OPCM_32_RR_IDIRECT */ enum { |