diff options
| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2015-05-06 20:57:10 +0200 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2015-05-22 17:02:33 +0200 |
| commit | ddd8cebe3106bdfb2681d8d283296199fd6c7417 (patch) | |
| tree | 107546dd46d1ee9d2ef85b14afc7b355d93a4e45 /target-tricore | |
| parent | 62872ebc38d700ea30b0cd861e40703dccdcae2a (diff) | |
target-tricore: add SWAPMSK instructions of the v1.6.1 ISA
Those instruction were introduced in the new Aurix platform.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-tricore')
| -rw-r--r-- | target-tricore/translate.c | 39 | ||||
| -rw-r--r-- | target-tricore/tricore-opcodes.h | 5 |
2 files changed, 44 insertions, 0 deletions
diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 06d183b146..b2e25e7c7f 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -333,6 +333,25 @@ static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea) tcg_temp_free(temp2); } +static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea) +{ + TCGv temp = tcg_temp_new(); + TCGv temp2 = tcg_temp_new(); + TCGv temp3 = tcg_temp_new(); + + tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); + tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]); + tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]); + tcg_gen_or_tl(temp2, temp2, temp3); + tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); + tcg_gen_mov_tl(cpu_gpr_d[reg], temp); + + tcg_temp_free(temp); + tcg_temp_free(temp2); + tcg_temp_free(temp3); +} + + /* We generate loads and store to core special function register (csfr) through the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3 makros R, A and E, which allow read-only, all and endinit protected access. @@ -5072,6 +5091,18 @@ static void decode_bo_addrmode_stctx_post_pre_base(CPUTriCoreState *env, tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); break; + case OPC2_32_BO_SWAPMSK_W_SHORTOFF: + tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); + gen_swapmsk(ctx, r1, temp); + break; + case OPC2_32_BO_SWAPMSK_W_POSTINC: + gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); + tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); + break; + case OPC2_32_BO_SWAPMSK_W_PREINC: + tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); + gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); + break; } tcg_temp_free(temp); tcg_temp_free(temp2); @@ -5123,6 +5154,14 @@ static void decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState *env, gen_cmpswap(ctx, r1, temp2); gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); break; + case OPC2_32_BO_SWAPMSK_W_BR: + gen_swapmsk(ctx, r1, temp2); + gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); + break; + case OPC2_32_BO_SWAPMSK_W_CIRC: + gen_swapmsk(ctx, r1, temp2); + gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); + break; } tcg_temp_free(temp); diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index 95837aa370..7ad6df9bd6 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -766,6 +766,9 @@ enum { OPC2_32_BO_CMPSWAP_W_SHORTOFF = 0x23, OPC2_32_BO_CMPSWAP_W_POSTINC = 0x03, OPC2_32_BO_CMPSWAP_W_PREINC = 0x13, + OPC2_32_BO_SWAPMSK_W_SHORTOFF = 0x22, + OPC2_32_BO_SWAPMSK_W_POSTINC = 0x02, + OPC2_32_BO_SWAPMSK_W_PREINC = 0x12, }; /*OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR */ enum { @@ -775,6 +778,8 @@ enum { OPC2_32_BO_SWAP_W_CIRC = 0x10, OPC2_32_BO_CMPSWAP_W_BR = 0x03, OPC2_32_BO_CMPSWAP_W_CIRC = 0x13, + OPC2_32_BO_SWAPMSK_W_BR = 0x02, + OPC2_32_BO_SWAPMSK_W_CIRC = 0x12, }; /* * BRC Format |