diff options
| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2015-04-03 14:29:22 +0200 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2015-05-11 14:15:46 +0200 |
| commit | 7bd0eaec311d188412123a034abb44595deb7dae (patch) | |
| tree | d964cfff24f44532537efaf0e6b004ed58ee4b87 /target-tricore | |
| parent | 250ef8c76861c756354ed1c67f0a4524e5339369 (diff) | |
target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory access insted of 4
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Diffstat (limited to 'target-tricore')
| -rw-r--r-- | target-tricore/translate.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-tricore/translate.c b/target-tricore/translate.c index d2cd64013d..663b2a0796 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -3745,10 +3745,10 @@ static void decode_slr_opc(DisasContext *ctx, int op1) tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); break; case OPC1_16_SLR_LD_W: - tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); + tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); break; case OPC1_16_SLR_LD_W_POSTINC: - tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); + tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); break; } |