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authorBastian Koppelmann <kbastian@mail.uni-paderborn.de>2015-05-11 14:59:55 +0200
committerBastian Koppelmann <kbastian@mail.uni-paderborn.de>2015-05-22 17:02:34 +0200
commit9371557115a734412974f8d4096cbe8a62ca2731 (patch)
tree7aedb471780d228438883c34b08fdc13084de5ea /target-tricore/tricore-opcodes.h
parent0e045f43c45f675711c3f6836118dc7eabcc2411 (diff)
target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-tricore/tricore-opcodes.h')
-rw-r--r--target-tricore/tricore-opcodes.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
index 22c79f570f..1bfed0ce48 100644
--- a/target-tricore/tricore-opcodes.h
+++ b/target-tricore/tricore-opcodes.h
@@ -1124,6 +1124,8 @@ enum {
OPC2_32_RR_PARITY = 0x02,
OPC2_32_RR_UNPACK = 0x08,
OPC2_32_RR_CRC32 = 0x03,
+ OPC2_32_RR_DIV = 0x20,
+ OPC2_32_RR_DIV_U = 0x21,
};
/* OPCM_32_RR_IDIRECT */
enum {