diff options
| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2015-01-19 15:05:01 +0000 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2015-01-27 11:48:02 +0000 |
| commit | 12f323e66e2d850b0e27300d609deae6e7290457 (patch) | |
| tree | ccb895c0d05640c4cafe61f3ddbe34bd606ba1a0 /target-tricore/translate.c | |
| parent | f1cc6eafdd08817a234e0e1a9c8f03177a31faf1 (diff) | |
target-tricore: Add instructions of RR2 opcode format
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-tricore/translate.c')
| -rw-r--r-- | target-tricore/translate.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 5e9eb283c5..ea0a2fc3d4 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -4958,6 +4958,39 @@ static void decode_rr1_mulq(CPUTriCoreState *env, DisasContext *ctx) tcg_temp_free(temp2); } +/* RR2 format */ +static void decode_rr2_mul(CPUTriCoreState *env, DisasContext *ctx) +{ + uint32_t op2; + int r1, r2, r3; + + op2 = MASK_OP_RR2_OP2(ctx->opcode); + r1 = MASK_OP_RR2_S1(ctx->opcode); + r2 = MASK_OP_RR2_S2(ctx->opcode); + r3 = MASK_OP_RR2_D(ctx->opcode); + switch (op2) { + case OPC2_32_RR2_MUL_32: + gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); + break; + case OPC2_32_RR2_MUL_64: + gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], + cpu_gpr_d[r2]); + break; + case OPC2_32_RR2_MULS_32: + gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], + cpu_gpr_d[r2]); + break; + case OPC2_32_RR2_MUL_U_64: + gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], + cpu_gpr_d[r2]); + break; + case OPC2_32_RR2_MULS_U_32: + gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], + cpu_gpr_d[r2]); + break; + } +} + static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) { int op1; @@ -5218,6 +5251,10 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) case OPCM_32_RR1_MULQ: decode_rr1_mulq(env, ctx); break; +/* RR2 format */ + case OPCM_32_RR2_MUL: + decode_rr2_mul(env, ctx); + break; } } |