diff options
| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2015-05-22 12:15:56 +0200 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2015-05-30 16:49:14 +0200 |
| commit | 05b6ca9bbcaede74120050aa8e6684300c09257c (patch) | |
| tree | d4445fb39cff5de21587ba44545fdc90c0a7469b /target-tricore/translate.c | |
| parent | 97af820f539efe80b87615a04f9de11ea585f725 (diff) | |
target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the result
If the argument r1 was the same as the extended result register r3+1, we would
overwrite r1 and then use it.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <1432289758-6250-2-git-send-email-kbastian@mail.uni-paderborn.de>
Diffstat (limited to 'target-tricore/translate.c')
| -rw-r--r-- | target-tricore/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 5f8eff04fa..6c14843438 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -6451,8 +6451,8 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) /* sv */ tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); /* write result */ - tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16); + tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); tcg_temp_free(temp); tcg_temp_free(temp2); tcg_temp_free(temp3); |