diff options
| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2016-02-16 22:33:13 +0100 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2016-02-25 12:51:27 +0100 |
| commit | 723733575b90089c51adefde41875310052031c2 (patch) | |
| tree | 93c75ade668085f0a8b570ac508f59bf838812ac /target-tricore/op_helper.c | |
| parent | d159148b63cb31ba086d26f1b7da24c0614ca856 (diff) | |
target-tricore: fix save_context_upper using env->PSW
If the cached bits for C, V, SV, AV, or SAV were set, they would
not be saved during the context save since env->PSW was stored instead
of properly reading them using psw_read().
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Diffstat (limited to 'target-tricore/op_helper.c')
| -rw-r--r-- | target-tricore/op_helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c index 3aa6326edd..796fe67cc8 100644 --- a/target-tricore/op_helper.c +++ b/target-tricore/op_helper.c @@ -2279,7 +2279,7 @@ static bool cdc_zero(target_ulong *psw) static void save_context_upper(CPUTriCoreState *env, int ea) { cpu_stl_data(env, ea, env->PCXI); - cpu_stl_data(env, ea+4, env->PSW); + cpu_stl_data(env, ea+4, psw_read(env)); cpu_stl_data(env, ea+8, env->gpr_a[10]); cpu_stl_data(env, ea+12, env->gpr_a[11]); cpu_stl_data(env, ea+16, env->gpr_d[8]); |