diff options
| author | Richard Henderson <rth@twiddle.net> | 2015-08-29 12:59:29 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2015-10-07 20:36:27 +1100 |
| commit | 667b8e29c5b1d8c5b4e6ad5f780ca60914eb6e96 (patch) | |
| tree | 0d1aa7775d9cb83ce858394f2e56114ccdc23f94 /target-tilegx | |
| parent | 765b842adec4c5a359e69ca08785553599f71496 (diff) | |
target-*: Unconditionally emit tcg_gen_insn_start
While we're at it, emit the opcode adjacent to where we currently
record data for search_pc. This puts gen_io_start et al on the
"correct" side of the marker.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-tilegx')
| -rw-r--r-- | target-tilegx/translate.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index 3fb7fc6a21..6babc3c733 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -2008,10 +2008,6 @@ static void translate_one_bundle(DisasContext *dc, uint64_t bundle) } dc->num_wb = 0; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { - tcg_gen_insn_start(dc->pc); - } - qemu_log_mask(CPU_LOG_TB_IN_ASM, " %" PRIx64 ": { ", dc->pc); if (get_Mode(bundle)) { notice_excp(dc, bundle, "y0", decode_y0(dc, bundle)); @@ -2100,6 +2096,8 @@ static inline void gen_intermediate_code_internal(TileGXCPU *cpu, tcg_ctx.gen_opc_instr_start[lj] = 1; tcg_ctx.gen_opc_icount[lj] = num_insns; } + tcg_gen_insn_start(dc->pc); + translate_one_bundle(dc, cpu_ldq_data(env, dc->pc)); if (dc->exit_tb) { |