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| author | Chen Gang <gang.chen.5i5j@gmail.com> | 2015-10-04 19:01:25 +0800 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2015-10-07 20:03:16 +1100 |
| commit | 78affcb798516dcb5d44a7ed598d79dcd42cd988 (patch) | |
| tree | b399780ae92c4338857986c3ba3f201f75890645 /target-tilegx | |
| parent | 133b84c819166a6da1425a007cf44d7a96d507a4 (diff) | |
target-tilegx: Implement v2sh* instructions
It is just according to v1sh* instructions implementation.
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Message-Id: <1443956491-26850-1-git-send-email-gang.chen.5i5j@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-tilegx')
| -rw-r--r-- | target-tilegx/translate.c | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index 6ab66f9b07..9bb8857876 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -1686,11 +1686,27 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext, break; case OE_SH(V2SHLI, X0): case OE_SH(V2SHLI, X1): + i2 = imm & 15; + i3 = 0xffff >> i2; + tcg_gen_andi_tl(tdest, tsrca, V2_IMM(i3)); + tcg_gen_shli_tl(tdest, tdest, i2); + mnemonic = "v2shli"; + break; case OE_SH(V2SHRSI, X0): case OE_SH(V2SHRSI, X1): + t0 = tcg_const_tl(imm & 15); + gen_helper_v2shrs(tdest, tsrca, t0); + tcg_temp_free(t0); + mnemonic = "v2shrsi"; + break; case OE_SH(V2SHRUI, X0): case OE_SH(V2SHRUI, X1): - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; + i2 = imm & 15; + i3 = (0xffff << i2) & 0xffff; + tcg_gen_andi_tl(tdest, tsrca, V2_IMM(i3)); + tcg_gen_shri_tl(tdest, tdest, i2); + mnemonic = "v2shrui"; + break; case OE(ADDLI_OPCODE_X0, 0, X0): case OE(ADDLI_OPCODE_X1, 0, X1): |