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authorblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2007-03-21 19:45:50 +0000
committerblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2007-03-21 19:45:50 +0000
commit9bad0425a0792b868eecfb9edd9157891554aa51 (patch)
treecbf6f70ac3f01bb0a647a7f12676e42899d1c72e /target-sparc
parent3953d7868768c179440e8302e536b436171205cc (diff)
Fix Sparc branches, original patch by Aurelien Jarno
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2523 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc')
-rw-r--r--target-sparc/translate.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 455dd171e4..74a0a2cb89 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -681,7 +681,7 @@ static inline void gen_mov_pc_npc(DisasContext * dc)
static GenOpFunc * const gen_cond[2][16] = {
{
- gen_op_eval_ba,
+ gen_op_eval_bn,
gen_op_eval_be,
gen_op_eval_ble,
gen_op_eval_bl,
@@ -689,7 +689,7 @@ static GenOpFunc * const gen_cond[2][16] = {
gen_op_eval_bcs,
gen_op_eval_bneg,
gen_op_eval_bvs,
- gen_op_eval_bn,
+ gen_op_eval_ba,
gen_op_eval_bne,
gen_op_eval_bg,
gen_op_eval_bge,
@@ -700,7 +700,7 @@ static GenOpFunc * const gen_cond[2][16] = {
},
{
#ifdef TARGET_SPARC64
- gen_op_eval_ba,
+ gen_op_eval_bn,
gen_op_eval_xbe,
gen_op_eval_xble,
gen_op_eval_xbl,
@@ -708,7 +708,7 @@ static GenOpFunc * const gen_cond[2][16] = {
gen_op_eval_xbcs,
gen_op_eval_xbneg,
gen_op_eval_xbvs,
- gen_op_eval_bn,
+ gen_op_eval_ba,
gen_op_eval_xbne,
gen_op_eval_xbg,
gen_op_eval_xbge,
@@ -722,7 +722,7 @@ static GenOpFunc * const gen_cond[2][16] = {
static GenOpFunc * const gen_fcond[4][16] = {
{
- gen_op_eval_ba,
+ gen_op_eval_bn,
gen_op_eval_fbne,
gen_op_eval_fblg,
gen_op_eval_fbul,
@@ -730,7 +730,7 @@ static GenOpFunc * const gen_fcond[4][16] = {
gen_op_eval_fbug,
gen_op_eval_fbg,
gen_op_eval_fbu,
- gen_op_eval_bn,
+ gen_op_eval_ba,
gen_op_eval_fbe,
gen_op_eval_fbue,
gen_op_eval_fbge,
@@ -741,7 +741,7 @@ static GenOpFunc * const gen_fcond[4][16] = {
},
#ifdef TARGET_SPARC64
{
- gen_op_eval_ba,
+ gen_op_eval_bn,
gen_op_eval_fbne_fcc1,
gen_op_eval_fblg_fcc1,
gen_op_eval_fbul_fcc1,
@@ -749,7 +749,7 @@ static GenOpFunc * const gen_fcond[4][16] = {
gen_op_eval_fbug_fcc1,
gen_op_eval_fbg_fcc1,
gen_op_eval_fbu_fcc1,
- gen_op_eval_bn,
+ gen_op_eval_ba,
gen_op_eval_fbe_fcc1,
gen_op_eval_fbue_fcc1,
gen_op_eval_fbge_fcc1,
@@ -759,7 +759,7 @@ static GenOpFunc * const gen_fcond[4][16] = {
gen_op_eval_fbo_fcc1,
},
{
- gen_op_eval_ba,
+ gen_op_eval_bn,
gen_op_eval_fbne_fcc2,
gen_op_eval_fblg_fcc2,
gen_op_eval_fbul_fcc2,
@@ -767,7 +767,7 @@ static GenOpFunc * const gen_fcond[4][16] = {
gen_op_eval_fbug_fcc2,
gen_op_eval_fbg_fcc2,
gen_op_eval_fbu_fcc2,
- gen_op_eval_bn,
+ gen_op_eval_ba,
gen_op_eval_fbe_fcc2,
gen_op_eval_fbue_fcc2,
gen_op_eval_fbge_fcc2,
@@ -777,7 +777,7 @@ static GenOpFunc * const gen_fcond[4][16] = {
gen_op_eval_fbo_fcc2,
},
{
- gen_op_eval_ba,
+ gen_op_eval_bn,
gen_op_eval_fbne_fcc3,
gen_op_eval_fblg_fcc3,
gen_op_eval_fbul_fcc3,
@@ -785,7 +785,7 @@ static GenOpFunc * const gen_fcond[4][16] = {
gen_op_eval_fbug_fcc3,
gen_op_eval_fbg_fcc3,
gen_op_eval_fbu_fcc3,
- gen_op_eval_bn,
+ gen_op_eval_ba,
gen_op_eval_fbe_fcc3,
gen_op_eval_fbue_fcc3,
gen_op_eval_fbge_fcc3,