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authorPaolo Bonzini <pbonzini@redhat.com>2016-10-06 15:10:57 +0200
committerPaolo Bonzini <pbonzini@redhat.com>2016-10-07 10:05:22 +0200
commitc3ce5a235741cb027b1328288ddec06470254813 (patch)
tree18b91ded381a74e17158c282dea2047b0ae3c3e6 /target-sparc
parentbf28a69eeb53e9e45166fbdda032454e7b1e3f29 (diff)
qemu-tech: document lazy condition code evaluation in cpu.h
Unlike the other sections, they are pretty specific to a particular CPU. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target-sparc')
-rw-r--r--target-sparc/cpu.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index a3d64a4e52..646a103513 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -102,6 +102,11 @@
#define CC_DST (env->cc_dst)
#define CC_OP (env->cc_op)
+/* Even though lazy evaluation of CPU condition codes tends to be less
+ * important on RISC systems where condition codes are only updated
+ * when explicitly requested, SPARC uses it to update 32-bit and 64-bit
+ * condition codes.
+ */
enum {
CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
CC_OP_FLAGS, /* all cc are back in status register */