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authorFabien Chouteau <chouteau@adacore.com>2011-01-31 11:36:54 +0100
committerBlue Swirl <blauwirbel@gmail.com>2011-02-01 17:01:41 +0000
commit60f356e86d66a4a22530ec7570f7582af602d200 (patch)
tree243b43a088e1cba43673a99edba65061dc162ce8 /target-sparc
parent2685d2961b51437d0c7bc71f4ed7c320f6cbd010 (diff)
SPARC: Fix Leon3 cache control
The "leon3_cache_control_int" (op_helper.c) function is called within leon3.c which leads to segfault error with the global "env". Now cache control is a CPU feature and everything is handled in op_helper.c. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-sparc')
-rw-r--r--target-sparc/cpu.h8
-rw-r--r--target-sparc/helper.c2
-rw-r--r--target-sparc/op_helper.c18
3 files changed, 21 insertions, 7 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 6f5990b130..320530ec9f 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -268,6 +268,8 @@ typedef struct sparc_def_t {
#define CPU_FEATURE_GL (1 << 13)
#define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */
#define CPU_FEATURE_ASR17 (1 << 15)
+#define CPU_FEATURE_CACHE_CTRL (1 << 16)
+
#ifndef TARGET_SPARC64
#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
@@ -476,12 +478,14 @@ void cpu_put_cwp64(CPUState *env1, int cwp);
int cpu_cwp_inc(CPUState *env1, int cwp);
int cpu_cwp_dec(CPUState *env1, int cwp);
void cpu_set_cwp(CPUState *env1, int new_cwp);
-
-void leon3_cache_control_int(void);
+void leon3_irq_manager(void *irq_manager, int intno);
/* sun4m.c, sun4u.c */
void cpu_check_irqs(CPUSPARCState *env);
+/* leon3.c */
+void leon3_irq_ack(void *irq_manager, int intno);
+
#if defined (TARGET_SPARC64)
static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask)
diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index 2f3d1e61f3..b2d4d70a11 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -1289,7 +1289,7 @@ static const sparc_def_t sparc_defs[] = {
.mmu_trcr_mask = 0xffffffff,
.nwindows = 8,
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN |
- CPU_FEATURE_ASR17,
+ CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL,
},
#endif
};
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index d3e1b63539..854f168c60 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -1653,7 +1653,7 @@ static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
/* Leon3 cache control */
-void leon3_cache_control_int(void)
+static void leon3_cache_control_int(void)
{
uint32_t state = 0;
@@ -1741,11 +1741,17 @@ static uint64_t leon3_cache_control_ld(target_ulong addr, int size)
DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
break;
};
- DPRINTF_CACHE_CONTROL("st addr:%08x, ret:%" PRIx64 ", size:%d\n",
+ DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n",
addr, ret, size);
return ret;
}
+void leon3_irq_manager(void *irq_manager, int intno)
+{
+ leon3_irq_ack(irq_manager, intno);
+ leon3_cache_control_int();
+}
+
uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
{
uint64_t ret = 0;
@@ -1760,7 +1766,9 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
case 0x00: /* Leon3 Cache Control */
case 0x08: /* Leon3 Instruction Cache config */
case 0x0C: /* Leon3 Date Cache config */
- ret = leon3_cache_control_ld(addr, size);
+ if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
+ ret = leon3_cache_control_ld(addr, size);
+ }
break;
case 0x01c00a00: /* MXCC control register */
if (size == 8)
@@ -1994,7 +2002,9 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
case 0x00: /* Leon3 Cache Control */
case 0x08: /* Leon3 Instruction Cache config */
case 0x0C: /* Leon3 Date Cache config */
- leon3_cache_control_st(addr, val, size);
+ if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
+ leon3_cache_control_st(addr, val, size);
+ }
break;
case 0x01c00000: /* MXCC stream data register 0 */