diff options
| author | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-06-15 18:06:39 +0000 |
|---|---|---|
| committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-06-15 18:06:39 +0000 |
| commit | 07bf2857b8517711b5af2c516208bf87c546419f (patch) | |
| tree | 23c9cb224661026847ca79e437e60d3e24565c97 /target-sparc | |
| parent | 2daf028464375416f1461710c95522890968f4f2 (diff) | |
Avoid temporary variable use across basic blocks for udivx
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4744 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc')
| -rw-r--r-- | target-sparc/translate.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 999378a6d0..a821ef3f3e 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -3068,8 +3068,10 @@ static void disas_sparc_insn(DisasContext * dc) break; #ifdef TARGET_SPARC64 case 0xd: /* V9 udivx */ - gen_trap_ifdivzero_tl(cpu_src2); - tcg_gen_divu_i64(cpu_dst, cpu_src1, cpu_src2); + tcg_gen_mov_tl(cpu_cc_src, cpu_src1); + tcg_gen_mov_tl(cpu_cc_src2, cpu_src2); + gen_trap_ifdivzero_tl(cpu_cc_src2); + tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2); break; #endif case 0xe: |