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authorblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2008-09-11 16:01:02 +0000
committerblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2008-09-11 16:01:02 +0000
commit5068cbd9e9ef1bec70b5c04650a12d8d8bb7ff3d (patch)
tree906fa64307f3b39cad91e27b35c822f897ac3a86 /target-sparc
parent2c41a5f9e355412bdab3d92329ae5637bbdb08f1 (diff)
Write zeros to high bits of y, based on patch by Vince Weaver
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5196 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc')
-rw-r--r--target-sparc/translate.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 3d7d958b76..fc28aebef4 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -709,7 +709,8 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
tcg_gen_shli_tl(r_temp, r_temp, 31);
tcg_gen_shri_tl(cpu_tmp0, cpu_y, 1);
- tcg_gen_or_tl(cpu_y, cpu_tmp0, r_temp);
+ tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp);
+ tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
// b1 = N ^ V;
gen_mov_reg_N(cpu_tmp0, cpu_psr);
@@ -3195,7 +3196,8 @@ static void disas_sparc_insn(DisasContext * dc)
{
switch(rd) {
case 0: /* wry */
- tcg_gen_xor_tl(cpu_y, cpu_src1, cpu_src2);
+ tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
+ tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
break;
#ifndef TARGET_SPARC64
case 0x01 ... 0x0f: /* undefined in the