diff options
| author | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-04-23 17:12:35 +0000 |
|---|---|---|
| committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-04-23 17:12:35 +0000 |
| commit | 4b8b8b76d460804c7318a85cfe5352876f2430f7 (patch) | |
| tree | c05533da03a69b8e39f27e6d2ea56948c55008d5 /target-sparc | |
| parent | a23a663b6555497b1569e407cc8edff09787decb (diff) | |
Document the shift values
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4243 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc')
| -rw-r--r-- | target-sparc/cpu.h | 18 | ||||
| -rw-r--r-- | target-sparc/translate.c | 12 |
2 files changed, 18 insertions, 12 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 2002a05dea..fee26981e6 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -71,10 +71,14 @@ #define TT_TRAP 0x100 #endif -#define PSR_NEG (1<<23) -#define PSR_ZERO (1<<22) -#define PSR_OVF (1<<21) -#define PSR_CARRY (1<<20) +#define PSR_NEG_SHIFT 23 +#define PSR_NEG (1 << PSR_NEG_SHIFT) +#define PSR_ZERO_SHIFT 22 +#define PSR_ZERO (1 << PSR_ZERO_SHIFT) +#define PSR_OVF_SHIFT 21 +#define PSR_OVF (1 << PSR_OVF_SHIFT) +#define PSR_CARRY_SHIFT 20 +#define PSR_CARRY (1 << PSR_CARRY_SHIFT) #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY) #define PSR_EF (1<<12) #define PSR_PIL 0xf00 @@ -141,8 +145,10 @@ #define FSR_FTT_SEQ_ERROR (4 << 14) #define FSR_FTT_INVAL_FPR (6 << 14) -#define FSR_FCC1 (1<<11) -#define FSR_FCC0 (1<<10) +#define FSR_FCC1_SHIFT 11 +#define FSR_FCC1 (1 << FSR_FCC1_SHIFT) +#define FSR_FCC0_SHIFT 10 +#define FSR_FCC0 (1 << FSR_FCC0_SHIFT) /* MMU */ #define MMU_E (1<<0) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 90d9278152..2e38f84216 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -266,28 +266,28 @@ static inline void gen_goto_tb(DisasContext *s, int tb_num, static inline void gen_mov_reg_N(TCGv reg, TCGv src) { tcg_gen_extu_i32_tl(reg, src); - tcg_gen_shri_tl(reg, reg, 23); + tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT); tcg_gen_andi_tl(reg, reg, 0x1); } static inline void gen_mov_reg_Z(TCGv reg, TCGv src) { tcg_gen_extu_i32_tl(reg, src); - tcg_gen_shri_tl(reg, reg, 22); + tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT); tcg_gen_andi_tl(reg, reg, 0x1); } static inline void gen_mov_reg_V(TCGv reg, TCGv src) { tcg_gen_extu_i32_tl(reg, src); - tcg_gen_shri_tl(reg, reg, 21); + tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT); tcg_gen_andi_tl(reg, reg, 0x1); } static inline void gen_mov_reg_C(TCGv reg, TCGv src) { tcg_gen_extu_i32_tl(reg, src); - tcg_gen_shri_tl(reg, reg, 20); + tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT); tcg_gen_andi_tl(reg, reg, 0x1); } @@ -965,7 +965,7 @@ static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src, unsigned int fcc_offset) { tcg_gen_extu_i32_tl(reg, src); - tcg_gen_shri_tl(reg, reg, 10 + fcc_offset); + tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset); tcg_gen_andi_tl(reg, reg, 0x1); } @@ -973,7 +973,7 @@ static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src, unsigned int fcc_offset) { tcg_gen_extu_i32_tl(reg, src); - tcg_gen_shri_tl(reg, reg, 11 + fcc_offset); + tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset); tcg_gen_andi_tl(reg, reg, 0x1); } |