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authorblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2007-12-10 19:58:20 +0000
committerblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2007-12-10 19:58:20 +0000
commit666c87aa3b91298ab3b57da6c2ad63b526703b40 (patch)
treea5f20477ebf88b4c4183141e58130e50365f6f1a /target-sparc
parente32448e059adc8e6b31df483a679b399bc990e5a (diff)
Add ASIs (Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3801 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc')
-rw-r--r--target-sparc/op_helper.c9
1 files changed, 8 insertions, 1 deletions
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index a71c9da370..b711c6273e 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -411,6 +411,9 @@ void helper_ld_asi(int asi, int size, int sign)
break;
}
break;
+ case 0x39: /* data cache diagnostic register */
+ ret = 0;
+ break;
case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
default:
do_unassigned_access(T0, 0, 0, 1);
@@ -703,9 +706,13 @@ void helper_st_asi(int asi, int size)
}
}
return;
- case 0x31: /* Ross RT620 I-cache flush */
+ case 0x30: /* store buffer tags */
+ case 0x31: /* store buffer data or Ross RT620 I-cache flush */
+ case 0x32: /* store buffer control */
case 0x36: /* I-cache flash clear */
case 0x37: /* D-cache flash clear */
+ case 0x38: /* breakpoint diagnostics */
+ case 0x4c: /* breakpoint action */
break;
case 9: /* Supervisor code access, XXX */
case 0x21 ... 0x2d: /* MMU passthrough, unassigned */