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authorblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2008-05-31 11:33:20 +0000
committerblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2008-05-31 11:33:20 +0000
commitb5154bdedb1c390ec77ed97bf369ece27c50f4bc (patch)
tree948320e4d4ecec9d9de7179e3badc8d8a5409606 /target-sparc
parentc4d918070d08fd990cac68b5345138bd0ecfaf87 (diff)
Add more SuperSparcs
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4633 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc')
-rw-r--r--target-sparc/helper.c36
1 files changed, 36 insertions, 0 deletions
diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index 4537314d69..bf74c0d293 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -1214,6 +1214,30 @@ static const sparc_def_t sparc_defs[] = {
.features = CPU_DEFAULT_FEATURES,
},
{
+ .name = "TI SuperSparc 40", // STP1020NPGA
+ .iu_version = 0x41000000,
+ .fpu_version = 0 << 17,
+ .mmu_version = 0x00000000,
+ .mmu_bm = 0x00002000,
+ .mmu_ctpr_mask = 0xffffffc0,
+ .mmu_cxr_mask = 0x0000ffff,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "TI SuperSparc 50", // STP1020PGA
+ .iu_version = 0x40000000,
+ .fpu_version = 0 << 17,
+ .mmu_version = 0x04000000,
+ .mmu_bm = 0x00002000,
+ .mmu_ctpr_mask = 0xffffffc0,
+ .mmu_cxr_mask = 0x0000ffff,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
.name = "TI SuperSparc 51",
.iu_version = 0x43000000,
.fpu_version = 0 << 17,
@@ -1226,6 +1250,18 @@ static const sparc_def_t sparc_defs[] = {
.features = CPU_DEFAULT_FEATURES,
},
{
+ .name = "TI SuperSparc 60", // STP1020APGA
+ .iu_version = 0x40000000,
+ .fpu_version = 0 << 17,
+ .mmu_version = 0x03000000,
+ .mmu_bm = 0x00002000,
+ .mmu_ctpr_mask = 0xffffffc0,
+ .mmu_cxr_mask = 0x0000ffff,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
.name = "TI SuperSparc 61",
.iu_version = 0x44000000,
.fpu_version = 0 << 17,