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authorblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2008-09-03 17:32:10 +0000
committerblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2008-09-03 17:32:10 +0000
commite83ce550688af60cd5f5f78db4071eaa4858065f (patch)
tree5bf62b37184da61e00af55e901c6c5b6fead7b89 /target-sparc
parent4487fd349baa6d2ae34ab86dea843642d20a036a (diff)
Implement no-fault loads
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5148 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc')
-rw-r--r--target-sparc/op_helper.c44
1 files changed, 36 insertions, 8 deletions
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index 47cd998ac4..75020a92f2 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -1402,10 +1402,17 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
address_mask(env, &addr);
switch (asi) {
- case 0x80: // Primary
case 0x82: // Primary no-fault
- case 0x88: // Primary LE
case 0x8a: // Primary no-fault LE
+ if (page_check_range(addr, size, PAGE_READ) == -1) {
+#ifdef DEBUG_ASI
+ dump_asi("read ", last_addr, asi, size, ret);
+#endif
+ return 0;
+ }
+ // Fall through
+ case 0x80: // Primary
+ case 0x88: // Primary LE
{
switch(size) {
case 1:
@@ -1424,10 +1431,17 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
}
}
break;
- case 0x81: // Secondary
case 0x83: // Secondary no-fault
- case 0x89: // Secondary LE
case 0x8b: // Secondary no-fault LE
+ if (page_check_range(addr, size, PAGE_READ) == -1) {
+#ifdef DEBUG_ASI
+ dump_asi("read ", last_addr, asi, size, ret);
+#endif
+ return 0;
+ }
+ // Fall through
+ case 0x81: // Secondary
+ case 0x89: // Secondary LE
// XXX
break;
default:
@@ -1564,12 +1578,19 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
helper_check_align(addr, size - 1);
switch (asi) {
+ case 0x82: // Primary no-fault
+ case 0x8a: // Primary no-fault LE
+ if (cpu_get_phys_page_debug(env, addr) == -1ULL) {
+#ifdef DEBUG_ASI
+ dump_asi("read ", last_addr, asi, size, ret);
+#endif
+ return 0;
+ }
+ // Fall through
case 0x10: // As if user primary
case 0x18: // As if user primary LE
case 0x80: // Primary
- case 0x82: // Primary no-fault
case 0x88: // Primary LE
- case 0x8a: // Primary no-fault LE
if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
if ((env->def->features & CPU_FEATURE_HYPV)
&& env->hpstate & HS_PRIV) {
@@ -1650,15 +1671,22 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
// Only ldda allowed
raise_exception(TT_ILL_INSN);
return 0;
+ case 0x83: // Secondary no-fault
+ case 0x8b: // Secondary no-fault LE
+ if (cpu_get_phys_page_debug(env, addr) == -1ULL) {
+#ifdef DEBUG_ASI
+ dump_asi("read ", last_addr, asi, size, ret);
+#endif
+ return 0;
+ }
+ // Fall through
case 0x04: // Nucleus
case 0x0c: // Nucleus Little Endian (LE)
case 0x11: // As if user secondary
case 0x19: // As if user secondary LE
case 0x4a: // UPA config
case 0x81: // Secondary
- case 0x83: // Secondary no-fault
case 0x89: // Secondary LE
- case 0x8b: // Secondary no-fault LE
// XXX
break;
case 0x45: // LSU