diff options
| author | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-02-27 17:44:03 +0000 |
|---|---|---|
| committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-02-27 17:44:03 +0000 |
| commit | b25deda7ca528d8658304bed0479c9609add061e (patch) | |
| tree | 0d5530ac173ee80f65f6b85fa080d8c5b7ce9171 /target-sparc | |
| parent | 77b087cd27dd95a71d246f1e97fbaaea4ed3f1c1 (diff) | |
Temporary fix for i386 host
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3994 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc')
| -rw-r--r-- | target-sparc/op_mem.h | 10 | ||||
| -rw-r--r-- | target-sparc/translate.c | 17 |
2 files changed, 27 insertions, 0 deletions
diff --git a/target-sparc/op_mem.h b/target-sparc/op_mem.h index 9e1a9c25f3..a95c733ed0 100644 --- a/target-sparc/op_mem.h +++ b/target-sparc/op_mem.h @@ -4,6 +4,16 @@ #define ADDR(x) (x) #endif +#ifdef __i386__ +/*** Integer store ***/ +void OPPROTO glue(op_std, MEMSUFFIX)(void) +{ + uint64_t tmp = ((uint64_t)T1 << 32) | (uint64_t)(T2 & 0xffffffff); + + glue(stq, MEMSUFFIX)(ADDR(T0), tmp); +} + +#endif /* __i386__ */ /*** Floating-point store ***/ void OPPROTO glue(op_stf, MEMSUFFIX) (void) { diff --git a/target-sparc/translate.c b/target-sparc/translate.c index fd896855e9..b93a0875ea 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -192,6 +192,9 @@ GEN32(gen_op_store_QT1_fpr, gen_op_store_QT1_fpr_fprf); #endif #ifndef CONFIG_USER_ONLY +#ifdef __i386__ +OP_LD_TABLE(std); +#endif /* __i386__ */ OP_LD_TABLE(stf); OP_LD_TABLE(stdf); OP_LD_TABLE(ldf); @@ -231,6 +234,13 @@ static inline void gen_movl_reg_T1(int reg) gen_movl_reg_TN(reg, cpu_T[1]); } +#ifdef __i386__ +static inline void gen_movl_reg_T2(int reg) +{ + gen_movl_reg_TN(reg, cpu_T[2]); +} + +#endif /* __i386__ */ static inline void gen_movl_TN_reg(int reg, TCGv tn) { if (reg == 0) @@ -3275,6 +3285,7 @@ static void disas_sparc_insn(DisasContext * dc) case 0x7: /* store double word */ if (rd & 1) goto illegal_insn; +#ifndef __i386__ else { TCGv r_dword, r_low; @@ -3286,6 +3297,12 @@ static void disas_sparc_insn(DisasContext * dc) r_low); tcg_gen_qemu_st64(r_dword, cpu_T[0], dc->mem_idx); } +#else /* __i386__ */ + gen_op_check_align_T0_7(); + flush_T2(dc); + gen_movl_reg_T2(rd + 1); + gen_op_ldst(std); +#endif /* __i386__ */ break; #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) case 0x14: /* store word alternate */ |