diff options
| author | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-09-22 19:50:28 +0000 |
|---|---|---|
| committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-09-22 19:50:28 +0000 |
| commit | 9d92659858e5dfad56148586f5d2351178223979 (patch) | |
| tree | 6cd6ae859380ab94bcc4d37016de0a2da02f3cdc /target-sparc/translate.c | |
| parent | d3ae49bcf77c7604447ab3e1e90a0df0b539afaa (diff) | |
Add software and timer interrupt support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5299 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc/translate.c')
| -rw-r--r-- | target-sparc/translate.c | 34 |
1 files changed, 29 insertions, 5 deletions
diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 96dd56faa6..abea2f15a2 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -49,7 +49,7 @@ static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val; #ifdef TARGET_SPARC64 static TCGv cpu_xcc, cpu_asi, cpu_fprs, cpu_gsr; static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr; -static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver; +static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver, cpu_softint; #else static TCGv cpu_wim; #endif @@ -2102,6 +2102,10 @@ static void disas_sparc_insn(DisasContext * dc) goto jmp_insn; gen_movl_TN_reg(rd, cpu_gsr); break; + case 0x16: /* Softint */ + tcg_gen_ext_i32_tl(cpu_dst, cpu_softint); + gen_movl_TN_reg(rd, cpu_dst); + break; case 0x17: /* Tick compare */ gen_movl_TN_reg(rd, cpu_tick_cmpr); break; @@ -2126,7 +2130,6 @@ static void disas_sparc_insn(DisasContext * dc) case 0x12: /* Dispatch Control */ case 0x14: /* Softint set, WO */ case 0x15: /* Softint clear, WO */ - case 0x16: /* Softint write */ #endif default: goto illegal_insn; @@ -3233,6 +3236,27 @@ static void disas_sparc_insn(DisasContext * dc) goto jmp_insn; tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2); break; + case 0x14: /* Softint set */ + if (!supervisor(dc)) + goto illegal_insn; + tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2); + tcg_gen_helper_0_1(helper_set_softint, + cpu_tmp64); + break; + case 0x15: /* Softint clear */ + if (!supervisor(dc)) + goto illegal_insn; + tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2); + tcg_gen_helper_0_1(helper_clear_softint, + cpu_tmp64); + break; + case 0x16: /* Softint write */ + if (!supervisor(dc)) + goto illegal_insn; + tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2); + tcg_gen_helper_0_1(helper_write_softint, + cpu_tmp64); + break; case 0x17: /* Tick compare */ #if !defined(CONFIG_USER_ONLY) if (!supervisor(dc)) @@ -3292,9 +3316,6 @@ static void disas_sparc_insn(DisasContext * dc) case 0x11: /* Performance Instrumentation Counter */ case 0x12: /* Dispatch Control */ - case 0x14: /* Softint set */ - case 0x15: /* Softint clear */ - case 0x16: /* Softint write */ #endif default: goto illegal_insn; @@ -4952,6 +4973,9 @@ void gen_intermediate_code_init(CPUSPARCState *env) offsetof(CPUState, ssr), "ssr"); cpu_ver = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, offsetof(CPUState, version), "ver"); + cpu_softint = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, + offsetof(CPUState, softint), + "softint"); #else cpu_wim = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, offsetof(CPUState, wim), |