diff options
| author | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-03-18 18:06:54 +0000 |
|---|---|---|
| committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-03-18 18:06:54 +0000 |
| commit | 1f5063fb9756805efcd8c5a438ab747f36f796d9 (patch) | |
| tree | 3d02c12721ab1b323f519084dc220e2f7e6d82ad /target-sparc/translate.c | |
| parent | eb24dadde5f62b532bb887ba38e468f65692d96b (diff) | |
Convert array8/16/32 and alignaddr to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4085 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc/translate.c')
| -rw-r--r-- | target-sparc/translate.c | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/target-sparc/translate.c b/target-sparc/translate.c index cee85c4d81..7032dab115 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -3515,25 +3515,31 @@ static void disas_sparc_insn(DisasContext * dc) case 0x010: /* VIS I array8 */ gen_movl_reg_T0(rs1); gen_movl_reg_T1(rs2); - gen_op_array8(); + tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0], + cpu_T[1]); gen_movl_T0_reg(rd); break; case 0x012: /* VIS I array16 */ gen_movl_reg_T0(rs1); gen_movl_reg_T1(rs2); - gen_op_array16(); + tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0], + cpu_T[1]); + tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 1); gen_movl_T0_reg(rd); break; case 0x014: /* VIS I array32 */ gen_movl_reg_T0(rs1); gen_movl_reg_T1(rs2); - gen_op_array32(); + tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0], + cpu_T[1]); + tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 2); gen_movl_T0_reg(rd); break; case 0x018: /* VIS I alignaddr */ gen_movl_reg_T0(rs1); gen_movl_reg_T1(rs2); - gen_op_alignaddr(); + tcg_gen_helper_1_2(helper_alignaddr, cpu_T[0], cpu_T[0], + cpu_T[1]); gen_movl_T0_reg(rd); break; case 0x019: /* VIS II bmask */ |