diff options
| author | Richard Henderson <rth@twiddle.net> | 2012-10-16 19:32:24 +1000 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-10-20 07:56:07 +0000 |
| commit | f8641947c2268eab6e73f16883c08ae14432280c (patch) | |
| tree | 16e56e4e392e08067f9771307085481f39533e11 /target-sparc/translate.c | |
| parent | 7b9e066b67c1f8839a1ca63efebcbaf48cc60104 (diff) | |
target-sparc: Tidy ldfsr, stfsr
Remove the last uses of cpu_tmp32. Unify the code between sparc64
and sparc32 by using the proper "tl" functions.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-sparc/translate.c')
| -rw-r--r-- | target-sparc/translate.c | 37 |
1 files changed, 17 insertions, 20 deletions
diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 353ebc60a4..ed341b896f 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -60,7 +60,6 @@ static TCGv cpu_wim; #endif /* local register indexes (only used inside old micro ops) */ static TCGv cpu_tmp0; -static TCGv_i32 cpu_tmp32; static TCGv_i64 cpu_tmp64; /* Floating point registers */ static TCGv_i64 cpu_fpr[TARGET_DPREGS]; @@ -4834,17 +4833,15 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) if (rd == 1) { tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx); gen_helper_ldxfsr(cpu_env, cpu_tmp64); - } else { - tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx); - tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); - gen_helper_ldfsr(cpu_env, cpu_tmp32); + break; } -#else +#endif { - tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx); - gen_helper_ldfsr(cpu_env, cpu_tmp32); + TCGv_i32 t32 = get_temp_i32(dc); + tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx); + tcg_gen_trunc_tl_i32(t32, cpu_tmp0); + gen_helper_ldfsr(cpu_env, t32); } -#endif break; case 0x22: /* ldqf, load quad fpreg */ { @@ -4979,17 +4976,19 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) tcg_gen_qemu_st32(cpu_tmp0, cpu_addr, dc->mem_idx); break; case 0x25: /* stfsr, V9 stxfsr */ + { + TCGv t = get_temp_tl(dc); + + tcg_gen_ld_tl(t, cpu_env, offsetof(CPUSPARCState, fsr)); #ifdef TARGET_SPARC64 - gen_address_mask(dc, cpu_addr); - tcg_gen_ld_i64(cpu_tmp64, cpu_env, offsetof(CPUSPARCState, fsr)); - if (rd == 1) - tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx); - else - tcg_gen_qemu_st32(cpu_tmp64, cpu_addr, dc->mem_idx); -#else - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fsr)); - tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx); + gen_address_mask(dc, cpu_addr); + if (rd == 1) { + tcg_gen_qemu_st64(t, cpu_addr, dc->mem_idx); + break; + } #endif + tcg_gen_qemu_st32(t, cpu_addr, dc->mem_idx); + } break; case 0x26: #ifdef TARGET_SPARC64 @@ -5236,7 +5235,6 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb, insn = cpu_ldl_code(env, dc->pc); cpu_tmp0 = tcg_temp_new(); - cpu_tmp32 = tcg_temp_new_i32(); cpu_tmp64 = tcg_temp_new_i64(); cpu_dst = tcg_temp_new(); @@ -5245,7 +5243,6 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb, tcg_temp_free(cpu_dst); tcg_temp_free_i64(cpu_tmp64); - tcg_temp_free_i32(cpu_tmp32); tcg_temp_free(cpu_tmp0); if (dc->is_br) |